Synthesis in VLSI

What is Synthesis ? 

Synthesis refers to the process of transforming a high-level hardware description of a digital circuit into a gate-level representation. It involves converting an abstract description of the desired circuit behavior, typically written in a hardware description language (HDL) like Verilog or VHDL, into a network of logical gates and flip-flops.

So, in simple terms synthesis is Translation + Logic Optimization + Mapping.

Synthesis

Synthesis process is a crucial step in the VLSI design flow and serves as a bridge between the high-level design abstraction and the physical implementation. It involves several key tasks, including:

1. Parsing and elaboration: The synthesis tool reads the HDL code and performs syntax checking, building an abstract syntax tree. It also performs elaboration, which resolves references, checks for consistency, and prepares the design for subsequent transformations.

2. Optimization: The synthesis tool applies various optimization techniques to improve the circuit's characteristics, such as area, power consumption, and performance. These optimizations may involve logic restructuring, constant propagation, simplification, technology mapping, and other transformations.

3. Technology mapping: This step maps the abstract logic elements used in the high-level design to the specific gates available in the target technology library. It determines the most suitable gate-level representation based on the target technology's characteristics and constraints.

4. Timing constraints and optimization: Timing constraints, such as maximum delay, setup time, and hold time, are considered during synthesis. The tool analyzes the circuit's timing paths and optimizes them to meet the desired performance requirements.

5. Netlist generation: The output of synthesis is a gate-level netlist, which represents the circuit as a network of interconnected gates, flip-flops, and interconnect wires. The netlist can be further used for physical design steps, such as placement and routing.

It's important to note that synthesis is just one part of the overall VLSI design process, and it precedes physical design stages such as floorplanning, placement, and routing. The synthesized gate-level netlist serves as an input for these subsequent steps, leading to the final physical implementation of the integrated circuit.

Goals of Synthesis

The primary goals of synthesis in VLSI design are to transform a high-level hardware description into an optimized gate-level representation while meeting specific design objectives. The main objectives and goals of synthesis include:

Goals of Synthesis:

1. Functionality preservation

2. Optimization of design metrics

• Area optimization

• Power optimization

• Performance optimization

3. Technology mapping

4. Timing closure

5. Design scalability

Overall, the goals of synthesis revolve around achieving a functionally correct, optimized, and technology-mapped gate-level representation of the circuit that meets the desired design metrics and constraints.

Inputs and Outputs of Synthesis 

Inputs:

1. High-level Hardware Description

2. Constraints

3. Technology Library

Outputs:

1. Gate-Level Netlist

2. Optimized Design Metrics

3. Timing Constraints and Analysis

4. Constraints Check

Inputs & Outputs of Synthesis

Synthesis Flow

During the synthesis process in VLSI design, two crucial steps are HDL file generation and library setup. Let's explore each of these steps:

Synthesis Flow

1. HDL File Generation:

HDL (Hardware Description Language) file generation involves preparing the high-level hardware description in a suitable language such as Verilog or VHDL. The designer creates or writes the HDL code to describe the desired functionality and behavior of the digital circuit.

The HDL code is typically written using constructs that represent logical operations, data flow, and sequential behavior. It defines the modules, signals, registers, and other components required for the circuit. The code specifies how these components interact and function together to achieve the desired circuit behavior.

The HDL file can be created manually by the designer or generated by tools that assist in hardware design. The HDL code serves as the input for the synthesis tool, which transforms it into a gate-level representation.

2. Library Setup:

Library setup involves configuring the synthesis tool with the necessary information about the target technology library. The technology library contains a collection of pre-defined gates, flip-flops, and other elements available for use in the design. These elements are characterized by their electrical and logical properties, such as delay, power consumption, area, and functionality.

The library setup process typically includes the following steps:

a. Library Selection: The designer or synthesis tool selects the appropriate technology library based on the target technology, process node, and design requirements. Different libraries may have variations in performance, power consumption, or other characteristics, so choosing the most suitable library is essential.

b. Library Mapping: The synthesis tool maps the library elements to the corresponding elements used in the HDL code. For example, if the HDL code uses a logical AND gate, the synthesis tool maps it to the appropriate AND gate available in the library.

c. Technology Constraints: The library setup may involve specifying technology-specific constraints. These constraints can include maximum fan-out, maximum capacitance, power supply voltage, or any other limitations imposed by the target technology.

d. Characterization: The library setup may also include the characterization of library elements. This involves providing information about the delay, power, and area characteristics of the library elements to guide the synthesis tool's optimization process accurately.

By setting up the library, the synthesis tool gains knowledge of the available elements and their properties. This information guides the synthesis process, allowing the tool to make appropriate decisions for optimization, technology mapping, and achieving the desired design goals.

Commands for Specifying Libraries

• Link_library
• Target_library
• Symbol_library
• Synthetic_library

3.Read Design

Reading the design is an initial step in the synthesis flow, where the synthesis tool takes the high-level hardware description and performs various operations to analyze and prepare it for subsequent stages. Let's delve into the process of reading the design in the synthesis flow:

1. Parsing:

The synthesis tool starts by parsing the high-level hardware description, which is typically written in a hardware description language (HDL) such as Verilog or VHDL. Parsing involves analyzing the syntax and structure of the code to build an abstract syntax tree (AST). During parsing, the tool verifies that the code follows the grammar and rules of the chosen HDL.

2. Elaboration:

After parsing, the synthesis tool performs elaboration, which involves resolving references and dependencies in the design. It ensures that all components, modules, and signals are properly defined and instantiated, and that there are no unresolved references or inconsistencies. Elaboration prepares the design for subsequent transformations and optimizations.

3. Hierarchy Extraction:

The synthesis tool extracts the hierarchical structure of the design from the HDL code. It identifies modules, sub-modules, and their interconnections. This step is essential for understanding the organization and relationships between different parts of the design.

4. Logic Extraction:

The synthesis tool analyzes the logic described in the design to identify the data flow and control flow within the circuit. It identifies the logical operations, data dependencies, and control signals in order to optimize and map the design to the target technology library.

The reading phase in the synthesis flow provides the synthesis tool with a comprehensive understanding of the design's structure, logic, and constraints. This information serves as the foundation for subsequent optimization, technology mapping, and other transformations that occur during the synthesis process.

Commands for Reading the design

• Analyze
• Elaborate
• read_file

4.Define Design Environment

• Once the design have been read in, you need to define design environment and design constraints.It consists of Operating Conditions, Wire Load Models and System Interface requirements.It consists of Process, voltage and temperature requirements. The effect each of these can have on the chip need to be considered during synthesis and timing analysis.

• It allows DC to estimate the effect of wire length and fan out on resistance, capacitance and area of nets. DC uses these values to calculate wire delays. We use zero WLM when synthesis is done using DC.

• Wire load models are not needed when synthesis is done using DCT/DCG i.e. topographical mode. Net delays are estimated by virtual routing in DCT/DCG.

• The information regarding outside logic driving and receiving signals from your ASIC is captured through these constraints. It consists of Input drive strength (set_driving_cell), Capacitive load (set_load), output fan out load etc..report_lib, report_design are few of the commands to see the loaded environment constraints.

Commands to define design environment 

• Set_operating_condition
• Set_wire_load_model
• Set_drive
• Set_driving_cell
• Set_load
• Set_fanout_load
• Set_min_library

5. Set Design Constraints

These are two types of constraints. They are Design rule constraints and Design Optimization constraints.

1. The Design rule constraints are used to set the fannout, transition and capacitance values.Commands for setting Design Rule constraints are

• Set_max_fannout
• Set_max_transition
• Set_max_capacitance

2. Design Optimization constraints are to define a clock and its parameters, input and output delays, area etc. Commands to define design optimization constraints are

• Create_clock
• Set_clock_latency
• Set_clock_uncertainty
• set_propogated_clock
• set _input_delay
• Set_output_delay

6. Select Compile Strategy

Top-down and bottom-up are two different strategies used in the compilation or synthesis of a digital design. Let's explore each strategy:

Top-Down Compilation Strategy:

1. Top-down compilation, also known as top-down synthesis, starts with the high-level description of the design and proceeds towards the lower-level implementation. It follows a hierarchical approach where the design is divided into modules or blocks, and synthesis is performed on each module separately.In top-down compilation, the process begins with the highest-level module or the top-level module, which represents the entire design. The synthesis tool performs the synthesis on this module, transforming the high-level description into a gate-level representation. The tool then proceeds to the next lower-level modules and repeats the synthesis process for each module in a hierarchical manner.

Bottom-Up Compilation Strategy:

2. Bottom-up compilation, also known as bottom-up synthesis, takes an opposite approach to top-down synthesis. It starts with the lowest-level modules or components and progressively builds up to higher-level modules or the top-level design.In the bottom-up strategy, the synthesis tool initially performs synthesis on the individual lower-level modules or components. These modules may represent basic building blocks, such as adders, multipliers, or memory elements. Once the lower-level modules are synthesized, the tool proceeds to integrate them into higher-level modules, eventually synthesizing the complete design.

7. Design Optimization

1. Set_dont_touch , group paths are examples of design optimization techniques.

2. Using set_dont_touch , a sub design can be preserved.

3. The group_path command can be used to create path groups. The group_path command allows you to

• Control the optimization of your design

• Optimize near-critical paths

• Optimize all paths 

8. Generating the Reports

 After the design is optimized , reports must be generated. Analyzing these reports is necessary to further improve the design or to validate the current design.

Commands used to generate reports are

• Check_design
• Check_timing
• Report_area
• report_constraint

9. Save the Design

Finally, after the design is successfully compiled and analyzed , the file can be written using the write command.

Conclusion

Synthesis is essential for optimising performance, power usage, and efficient utilisation of space in VLSI design. Designers can improve their design analysis and make wise selections for effective circuit implementations by utilising a variety of methodologies and producing in-depth reports.