Concept to GDSII : Understanding the ASIC Design Process
ASIC Design Flow
ASICs or Application Specific Integrated Circuits are designed for specific purposes and are used in a variety of applications such as consumer electronics, automotive, aerospace, and many others. The ASIC design Process is a complex process that involves multiple stages and requires expertise in various fields such as digital and analog design, verification, physical design, and testing.
The ASIC flow can be divided into
the following major stages:
1. Specification and Architecture:
The first stage of ASIC design is
to define the specifications and architecture of the chip. This involves
understanding the requirements of the application and the system, and defining
the functionality of the chip. The specification also includes details on the
chip's performance, power consumption, and other requirements. A semiconductor
company's customer is often another business that intends to employ the chip in
their end goods or systems. So, when deciding how to design the chip, the needs
of the customer are also crucial. Naturally, gathering the requirements,
estimating the end product's market value, and assessing the quantity of
resources needed to complete the project would be the first steps
Here is an example of how
specifications of a chip design used for smart phones are given :
Ø
Performance:
High processing power and fast response times for demanding applications such
as gaming and video playback.
Ø
Power
Consumption: Efficient power management to extend battery life.
Ø
Area:
Small size to fit within the smartphone's form factor.
Ø
Operating
Environment: Temperature range of 0-35°C, operating frequency range of 800 MHz
to 2 GHz, and a voltage range of 1.0V to 1.5V.
Ø
Functional
Requirements: High-resolution camera support, image processing, audio
processing, and graphics rendering.
Ø
Reliability:
Error correction and fault tolerance to prevent data loss and system failure.
Ø
Security:
Encryption and authentication capabilities to protect sensitive data.
Ø
Cost:
Low cost to keep the overall product price competitive.
2. Design Entry:
3. Functional Verification:
After the RTL design has been
created, it needs to be verified to ensure that it meets the specification and
architecture requirements. This is done using functional verification, which
involves creating test benches and running simulations to verify the chip's
functionality. The goal of functional verification is to identify and fix any
design bugs before moving on to the next stage.
4. Synthesis:
Once the RTL design has been
verified, the next stage is synthesis. Synthesis involves converting the RTL
design into a gate-level netlist, which is a representation of the chip's
circuitry in terms of logic gates and their interconnections. The gate-level
netlist is then optimized for area, power, and timing.
5. Design Optimization:
The next stage is design
optimization, which involves improving the chip's performance, power
consumption, and area. This is done by applying various optimization techniques
such as clock tree synthesis, power optimization, and placement optimization.
6. Physical Design:
After the gate-level netlist has
been optimized, the next stage is physical design.Physical design is the stage
in chip design where the logic design is translated into an actual physical
layout of the chip, which is a set of interconnected transistors, wires, and
other components. This process involves converting the logical representation
of the chip's functionality, known as the netlist, into a physical design that
can be manufactured.This is a complex process that involves creating a
floorplan, placing the cells, routing the interconnections, and optimizing the
layout for timing, power, and area.
The physical design plays a
crucial role in chip design because it directly impacts the chip's performance,
power consumption, area, and manufacturing cost. The physical design is also a
critical step in the chip design flow because it determines the final layout of
the chip that will be used in the manufacturing process. Therefore, the
physical design process requires a high degree of accuracy, expertise, and
collaboration between the chip design team and the manufacturing team.
7. Timing Analysis:
Once the physical design is
complete, the next stage is timing analysis. Timing analysis involves ensuring
that the chip's circuits meet the timing requirements, which includes setup and
hold times, clock skew, and signal integrity.
Static Timing Analysis (STA) is a method of analyzing the timing behavior of a digital circuit without simulating its dynamic operation. It is a popular and widely used technique in VLSI design that evaluates the worst-case delay paths of the circuit to ensure that it meets its timing requirements. STA is performed at the gate-level or post-synthesis stage of the design flow and involves using various EDA (Electronic Design Automation) tools to analyze the circuit's timing behavior.
The main objective of STA is to
ensure that the circuit meets its timing requirements, such as setup time, hold
time, clock frequency, and maximum path delay. Timing requirements are usually
specified by the design team, based on the circuit's functional requirements
and performance goals. Timing violations can cause functional errors, signal
integrity issues, and reduced performance, and therefore, STA is crucial to
ensure the circuit's functionality and performance.
STA involves three main steps:
timing analysis, timing optimization, and timing closure. Here is a brief
overview of each step:
1. Timing Analysis: In this step,
the EDA tools analyze the worst-case delay paths of the circuit and evaluate
its timing behavior, such as critical path delay, slack, and timing violations.
The analysis results are used to identify the areas of the circuit that require
optimization.
2. Timing Optimization: In this
step, the EDA tools perform various optimizations to reduce the circuit's delay
and improve its performance. Timing optimization techniques include gate
sizing, buffer insertion, wire sizing, and clock tree synthesis.
3. Timing Closure: In this step,
the EDA tools perform additional timing analysis to ensure that the circuit
meets its timing requirements after optimization. If timing violations are
detected, the optimization process is repeated until the timing requirements
are met.
STA is a critical step in the
VLSI design flow, and it requires a high degree of accuracy, expertise, and
collaboration between the design team and the manufacturing team. STA is
essential for ensuring the circuit's functionality and performance, and it
helps to reduce the risk of timing violations during the manufacturing process.
8. Design Verification:
After the physical design and
timing analysis have been completed, the next stage is design verification.
This involves running a series of tests to ensure that the chip meets the
specification and architecture requirements. This is done using various
techniques such as simulation, formal verification, and emulation.
Design verification is a complex
process that involves multiple steps, including test planning, testbench
creation, simulation, formal verification, and hardware emulation. The goal of
design verification is to identify and correct errors in the digital circuit
design before it is manufactured, to ensure that the design meets its
functional and performance requirements. Design verification requires a high
degree of expertise, collaboration, and attention to detail, and it is critical
to the success of the VLSI design flow.
Here are the main types of
verification techniques used in VLSI design:
- Simulation: Simulation is the most widely used verification technique in VLSI design. It involves using software tools to simulate the behavior of the digital circuit under different test scenarios, such as input patterns and timing constraints. Simulation is useful for identifying functional errors, performance issues, and signal integrity problems.
- Formal Verification: Formal verification is a mathematically rigorous technique for verifying the correctness of a digital circuit design. Formal verification involves using mathematical models and logic proofs to prove that the design meets its functional and performance requirements. Formal verification is useful for verifying complex circuits and identifying design flaws that may not be detected by simulation.
- Hardware Emulation: Hardware emulation involves using hardware platforms to emulate the behavior of the digital circuit design. Hardware emulation is useful for testing and verifying the circuit's behavior under real-world conditions and identifying issues that may not be detected by simulation or formal methods.
9. Design for Testability:
The next stage is Design for
Testability (DFT), which involves adding additional circuits to the chip to
enable testing. It requires a high degree of expertise, collaboration, and
attention to detail. DFT helps to improve the quality and reliability of the
final product, reduce the cost of testing, and shorten the time-to-market. DFT
techniques are essential for ensuring that the digital circuit design is
testable, and faults or defects can be identified and corrected before the
final product is manufactured.
Here are some common DFT
techniques used in VLSI design:
- Scan Chain: Scan chain is a technique that involves inserting a shift register into the digital circuit design. The scan chain allows for the testing of the circuit by shifting test data into the circuit and then shifting the captured output data out of the circuit. The scan chain technique helps to identify faults or defects in the circuit, such as stuck-at faults, transition faults, and bridging faults.
- Built-In Self-Test (BIST): BIST is a technique that involves embedding a self-test circuit into the digital circuit design. The self-test circuit generates test patterns and evaluates the circuit's behavior to identify faults or defects. BIST helps to reduce the cost of testing and improve the quality and reliability of the final product.
- Boundary Scan: Boundary Scan is a technique that involves inserting a set of boundary scan cells around the digital circuit design. The boundary scan cells allow for the testing of the circuit by scanning test data into the circuit and then scanning the captured output data out of the circuit. Boundary Scan helps to identify faults or defects in the circuit, such as open circuits and short circuits.
- Functional Test Points: Functional test points are hardware points inserted into the digital circuit design to facilitate functional testing. Functional test points allow for the testing of the circuit by injecting test data into the circuit and then observing the output. Functional test points help to identify functional errors and performance issues in the circuit.
10. Manufacturing:
Once the design has been verified
and tested, the final stage is manufacturing. This involves fabricating the
chip onto a silicon wafer using a process called photolithography. The silicon
wafer is then cut into individual chips, which are packaged and tested before
being shipped to customers. The chip manufacturing industry is constantly
evolving, with new technologies and materials being developed to improve chip
performance, reduce power consumption, and increase manufacturing yields. The
industry is also driven by a continuous demand for smaller, faster, and more
powerful chips that can be used in a wide range of electronic devices, such as
smartphones, computers, and Internet of Things (IoT) devices.
Conclusion
In summary, the ASIC design flow is a complex process that involves multiple stages and requires expertise in various fields. The process starts with defining the specification and architecture, followed by design entry, functional verification, synthesis, design optimization, physical design, timing analysis, design verification, design for testability, and manufacturing. Each stage of the process is critical to the success of the manufacturing a chip.
